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80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c product specification 1995 jan 20 integrated circuits ic20 data handbook
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 2 1995 jan 20 description the 80cl410/83CL410 (hereafter generically referred to as 8xcl410) is manufactured in an advanced cmos process that allows the part to operate at supply voltages down to 1.8v and oscillator frequencies down to dc. the 8xcl410 has the same instruction set as the 80c51. the 8xcl410 features a 4k byte rom (83CL410), 128 bytes ram (both rom and ram are externally expandable to 64k bytes), four 8-bit ports, two 16-bit timer/counters, an i 2 c serial interface, a thirteen source, two priority level nested interrupt structure, and on-chip oscillator circuitry suitable for quartz crystal, ceramic resonator, rc, or lc. the 8xcl410 has two reduced power modes that are the same as those on the standard 80c51. the special reduced power feature of this part is that it can be stopped and then restarted. running from an external clock source, the clock can be stopped and after a period of time restarted. the 8xcl410 will resume operation from where it was when the code stopped with no loss of internal state, ram contents, or special function register contents. if the internal oscillator is used the part cannot be stopped and started, but the power-down mode, which can be terminated via an interrupt, can be used to achieve similar power savings and then restart without loss of on-chip ram and special function register values. features ? single supply voltage 1.8v to 6.0v ? frequency from dc to 12mhz ? 80c51 based architecture 4k 8 rom (64k external) 128 8 ram (64k external) four 8-bit i/o ports two 16-bit timer/counters a thirteen-source, two-level, nested priority interrupt structure 10 external interrupts ? fully static 80c51 cpu ? i 2 c serial interface ? two power control modes idle mode power-down mode can be terminated by reset or external interrupt ? wake-up via external interrupts at port 1 ? single supply voltage 1.8v to 6.0v ? frequency range of dc to 12mhz ? on-chip oscillator (quartz crystal, ceramic resonator, rc, lc) ? very low power consumption ? operating temperature range: 40 to +85 c pin configuration p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p2.5/a13 p2.6/a14 p2.7/a15 psen ale ea p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 v dd dip vso 20 21 v ss scl/int8/p1.6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 int2/p1.0 int3/p1.1 int4/p1.2 int5/p1.3 int6/p1.4 int7/p1.5 rst p3.0 p3.1 int0 /p3.2 int1 /p3.3 t0/p3.4 t1/p3.5 sda/int9/p1.7 wr /p3.6 rd /p3.7 xtal2 xtal1 44 34 1 11 33 23 12 22 qfp see next page for qfp pin functions. ordering code philips part order number part marking philips north america part order number 1 temperature c and package drawing number romless rom romless rom and package frequency n um b er p80cl410hfp p83CL410hfp p80cl410hf n p83CL410hf n 40 to +85, 40-pin plastic dual in-line package 32khz to 12mhz sot129-1 p80cl410hft p83CL410hft p80cl410hf d p83CL410hf d 40 to +85, 40-pin plastic very small outline package 32khz to 12mhz sot158-1 p83CL410hfh 40 to +85, 44-pin plastic quad flat pack 32khz to 12mhz sot307-2 note: 1. parts ordered by the philips north america part number will be marked with the philips part marking. for emulation purposes, the p85cl000 (piggyback version) with 256 bytes of ram is recommended.
port 0 port 1 port 2 port 3 address and data bus address bus alternate functions int0 int1 t0 t1 wr rd rst ea psen ale v ss v dd xtal1 xtal2 int2 int3 int4 int5 int6 int7 int8/scl int9/sda philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 3 plastic quad flat pack pin functions 44 34 1 11 33 23 12 22 qfp pin function pin function 1 p1.5/int7 23 p2.5/a13 2 p1.6/int8/scl 24 p2.6/a14 3 p1.7/int9/sda 25 p2.7/a15 4 rst 26 psen 5 p3.0 27 ale 6 nc 28 nc 7 p3.1 29 ea 8 p3.2/int0 30 p0.7/ad7 9 p3.3/int1 31 p0.6/ad6 10 p3.4/t0 32 p0.5/ad5 11 p3.5/t1 33 p0.4/ad4 12 p3.6/wr 34 p0.3/ad3 13 p3.7/rd 35 p0.2/ad2 14 xtal2 36 p0.1/ad1 15 xtal1 37 p0.0/ad0 16 v ss 38 v dd 17 nc 39 nc 18 p2.0/a8 40 p1.0/int2 19 p2.1/a9 41 p1.1/int3 20 p2.2/a10 42 p1.2/int4 21 p2.3/a11 43 p1.3/int5 22 p2.4/a12 44 p1.4/int6 logic symbol
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 4 block diagram 64k byte bus expansion contrtol programmable i/o cpu oscillator and timing two 16-bit timer/event counters t0 t1 counter (1) xtal2 xtal1 frequency reference internal interrupts external interrupts control parallel ports, address/data bus and i/o pins i 2 c-bus serial i/o (1) pins shared with parallel port pins. sda scl (1) (1) 10 3 data memory (128 8 ram) program memory (4k 8 rom)
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 5 pin description mnemonic pin no. type name and function mnemonic qfp dil40/ vso40 type name and function v ss 16 20 i ground: 0v reference. v dd 38 40 i power supply: this is the power supply voltage for normal, idle, and power-down operation. p0.00.7 3037 3932 i/o port 0: port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1s. p1.0p1.7 4044 13 18 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). additional functions include: 7 i/o scl (p1.6): i 2 c serial bus clock. 8 i/o sda (p1.7): i 2 c serial bus data. 18 i int2int9 (p1.0p1.7): additional external interrupts. p2.0p2.7 1825 2128 i/o port 2: port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application, it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses (mov @ri), port 2 emits the contents of the p2 special function register. p3.0p3.7 5, 713 1017 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: i il ). port 3 also serves the special features of the 80c51 family, as listed below: 8 12 i int0 (p3.2): external interrupt 0 9 13 i int1 (p3.3): external interrupt 1 10 14 i t0 (p3.4): timer 0 external input 11 15 i t1 (p3.5): timer 1 external input 12 16 o wr (p3.6): external data memory write strobe 13 17 o rd (p3.7): external data memory read strobe rst 4 9 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v dd . ale 27 30 o address latch enable: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. psen 26 29 o program store enable: the read strobe to external program memory. when the device is executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. ea 29 31 i external access enable: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to 0fffh. if ea is held high, the device executes from internal program memory unless the program counter contains an address greater than 0fffh. xtal1 15 19 i crystal 1: input to the inverting oscillator amplifier and input for an external clock source. xtal2 14 18 o crystal 2: output from the inverting oscillator amplifier.
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 6 table 1. 8xcl410 special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h dptr: dph dpl data pointer (2 bytes): high byte low byte 83h 82h 00h 00h bf be bd bc bb ba b9 b8 ip0*# interrupt priority 0 b8h ps1 pt1 px1 pt0 px0 xx000000b ff fe fd fc fb fa f9 f8 ip1*# interrupt priority 1 f8h px9 px8 px7 px6 px5 px4 px3 px2 00h af ae ad ac ab aa a9 a8 ien0*# interrupt enable 0 a8h ea es1 et1 ex1 et0 ex0 00h ef ee ed ec eb ea e9 e8 ien1*# interrupt enable 1 e8h ex9 ex8 ex7 ex6 ex5 ex4 ex3 ex2 00h c7 c6 c5 c4 c3 c2 c1 c0 irq1*# interrupt request flag c0h iq9 iq8 iq7 iq6 iq5 iq4 iq3 iq2 00h ix1# interrupt polarity e9h 00h p0* port 0 80h 87 86 85 84 83 82 81 80 ffh p1* port 1 90h 97 96 95 94 93 92 91 90 ffh p2* port 2 a0h a7 a6 a5 a4 a3 a2 a1 a0 ffh p3* port 3 b0h b7 b6 b5 b4 b3 b2 b1 b0 ffh pcon power control 87h smod gf1 gf0 pd idl 0xxx0000b d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov p 00h s1adr# slave address dbh 00h df de dd dc db da d9 d8 s1con*# serial control d8h ens1 sta sto si aa cr1 cr0 x0000000b s1dat# s1sta# serial data serial status dah d9h 00h 1111 1000b sp stack pointer 81h 07h 8f 8e 8d 8c 8b 8a 89 88 tcon* timer/counter con- trol 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h tmod timer/counter mode 89h gate c/t m1 m0 gate c/t m1 m0 00h th0 timer 0 high byte 8ch 00h th1 timer 1 high byte 8dh 00h tl0 timer 0 low byte 8ah 00h tl1 timer 1 low byte 8bh 00h * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs.
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 7 port options the pins of port 1 (not p1.6/scl or p1.7/sda), port 2, and port 3 may be individually configured with one of the following port options (see figure 1): option 1: standard port e quasi-bidirectional i/o with pull-up. the strong booster pull-up p1 is turned on for two oscillator periods after a 0-to-1 transition in the port latch. see figure 1(a). option 2: open drain equasi-bidirectional i/o with n-channel open drain output. use as an output requires the connection of an external pull-up resistor. see figure 1(b). option 3: push-pull eoutput with drive capability in both polarities. under this option, pins can only be used as outputs. see figure 1(c). the definition of port options for port 0 is slightly different. two cases have to be examined. first, accesses to external memory (ea = 0 or access above the built-in memory boundary), and second, i/o accesses. external memory accesses option 1: true 0 and 1 are written as address to the external memory (strong pull-up is used). option 2: an external pull-up resistor is needed for external accesses. option 3: not allowed for external memory accesses as the port can only be used as output. i/o accesses option 1: when writing a 1 to the port latch, the strong pull-up p1 will be on for two oscillator periods. no weak pull-up exists. without an external pull-up, this option can be used as a high-impedance input. option 2: open drainequasi-bidirectional i/o with n-channel open drain output. use as an output requires the connection of an external pull-up resistor. see figure 1(c). option 3: push-pulleoutput with drive capability in both polarities. under this option, pins can only be used as outputs. individual mask selection of the post-reset state is available on any of the above pins. make your selection by appending aso or aro to option 1, 2, or 3 above (e.g., 1s for a standard i/o to be set after reset or 2r for an open-drain i/o to be reset after reset. option s: set eafter reset, this pin will be initialized high. option r: reset eafter reset, this pin will be initialized low. figure 1. ports two oscillator periods q from port latch input data read port pin input buffer strong pull-up p1 n p2 p3 +5v i/o pin (a) q from port latch strong pull-up p1 n +5v i/o pin (c) i/o pin +5v external pull-up n q from port latch (b) input data read port pin input buffer
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 8 power-down mode the instruction setting pcon.1 is the last executed prior to going into the power-down mode. in power-down mode, the oscillator is stopped. the contents of the the on-chip ram and sfrs are preserved. the port pins output the values held by their respective sfrs. ale and psen are held low. in the power-down mode, v dd may be reduced to minimize power consumption. however, the supply voltage must not be reduced until the power-down mode is active, and must be restored before the hardware reset is applied and frees the oscillator. reset must be held active until the oscillator has restarted and stabilized. from the power-down mode the part can be restarted by using either the wake-up mode or the reset mode. wake-up mode setting both pd and idl bits in the pcon register forces the controller into the power-down mode. setting both bits enable the controller to be woken-up from the power-down mode via either an enabled external interrupt int2int9, or a reset operation. an external interrupt for an enabled interrupt int2int9 at port 1 starts both the oscillator and the delay counter. to ensure that the oscillator is stable before the controller restarts, the internal clock will remain inactive for 1536 oscillator periods after the interrupt is detected. this is controlled by the on-chip delay counter. after this, the pd flag will be reset, the controller is now in the idle mode and the interrupt will be handled in the normal way. reset mode setting only the pd bit in the pcon register again forces the controller into the power-down mode, but in this case it can only be restored to normal operation with a direct reset operation. to restore normal operation, the reset pin has to be kept high for a minimum of 24 oscillator periods. the on-chip delay counter is inactive. the user has to insure that the oscillator is stable before any operation is attempted. figure 2 illustrates the two possibilities for wake-up. idle mode the instruction that sets pcon.0 is the last instruction executed before going into idle mode. in idle mode, the internal clock is stopped for the cpu, but not for the interrupt, timer, and serial port functions. the cpu status is preserved along with the stack pointer, program counter, program status word and accumulator. the ram and all other registers maintain their data during idle mode. the port pins retain the logical states they held at idle mode activation. ale and psen hold at the logic high level. there are two methods used to terminate the idle mode. activation of any interrupt will cause pcon to be cleared by hardware; terminating idle mode. the interrupt is serviced, and following the instruction reti, the next instruction to be executed will be the one following the instruction that put the device in the the idle mode. flag bits gf0 and gf1 can be used to determine whether the interrupt was received during normal execution or idle mode. for example, the instruction that writes to pcon.0 can also set or clear one or both flag bits. when idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. the second method of terminating the idle mode is with an external hardware reset. since the oscillator is still running, the hardware reset is required to be active for only two machine cycles to complete the reset operation. reset redefines all sfrs, but does not affect the state of the on-chip ram. the status of the external pins during idle and power-down mode is shown in table 2. if the power-down mode is activated while accessing external memory, port data held in the special function register p2 is restored to port 2. if the data is a logic 1, the port pin is held high during the power-down mode. table 2. external pin status during idle and power-down modes mode program memory ale psen port 0 port 1 port 2 port 3 idle internal 1 1 data data data data idle external 1 1 floating data address data power-down internal 0 0 data data data data power-down external 0 0 floating data data data figure 2. wake-up operation > 24 periods delay counter 1536 periods power-down reset pin external interrupt oscillator
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 9 76 5 4 3 2 1 0 s1con 76 5 4 3 2 1 0 s1sta bus clock generator figure 3. serial i/o arbitration logic shift register s1dat slave address s1adr gc internal bus sda scl i 2 c-bus serial i/o the serial port supports the twin line i 2 c-bus. the i 2 c-bus consists of a data line (sda) and a clock line (scl). these lines also function as i/o port lines p1.7 and p1.6 respectively. the system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. the i 2 c-bus serial i/o has complete autonomy in byte handling and operates in four modes: master transmitter master receiver slave transmitter slave receiver these functions are controlled by the s1con register. s1sta is the status register whose contents may also be used as a vector to various service routines. s1dat is the data shift register and s1adr the slave address register. slave address recognition is performed by hardware. s1con (d8h) serial control register cr2 ens1 sta sto si aa cr1 cr0 cr0, cr1, cr2 these three bits determine the serial clock frequency when sio is in a master mode. aa assert acknowledge bit. when the aa flag is set, an acknowledge (low level to sda) will be returned during the acknowledge clock pulse on the scl line when: own slave address is received general call address is received (s1adr.0 = 1) data byte received while device is programmed as master data byte received while device is selected slave with aa = 0, no acknowledge will be returned. consequently, no interrupt is requested when the aown slave addresso or general call address is received. si sio interrupt flag. when the si flag is set, an acknowledge is returned after any one of the following conditions: a start condition is generated in master mode own slave address received during aa = 1 general call address received while s1adr.0 and aa = 1 data byte received or transmitted in master mode (even if arbitration is lost) data byte received or transmitted as selected slave stop or start condition received as selected slave receiver or transmitter sto stop flag. with this bit set while in master mode, a stop condition is generated. when a stop condition is detected on the bus, the sio hardware clears the sto flag. in the slave mode, the sto flag may also be set to recover from an error condition. in this case, no stop condition is transmitted to the i 2 c-bus. however, the sio hardware behaves as if a stop condition has been received and releases sda and scl. the sio then switches to the anot addressedo slave receiver mode. the sto flag is automatically cleared by hardware. sta start flag. when the sta bit is set in slave mode, the sio hardware checks the status of the i 2 c-bus and generates a start condition if the bus is free. if sta is set while the sio is in master mode, sio transmits a repeated start condition. ens1 when ens1 = 0, the sio is disabled. the sda and scl outputs are in a high-impedance state; p1.6 and p1.7 function as open drain ports. when ens1 = 1, the sio is enabled. the p1.6 and p1.7 port latches must be set to logic 1.
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 10 s1sta (d9h) status register sc4 sc3 sc2 sc1 sc0 0 0 0 s1sta is an 8-bit read-only special function register. s1sta.3s1sta.7 hold a status code. s1sta.0s1sta.2 are held low. the contents of s1sta may be used as a vector to a service routine. this optimizes response time of the software and consequently that of the i 2 c-bus. the following is a list of the status codes: abbreviations used: sla: 7-bit slave address r: read bit w: write bit ack : acknowledgement (acknowledge bit = 0) ack: not acknowledge (acknowledge bit = 1) data: 8-bit byte to or from the i 2 c-bus mst: master slv: slave trx: transmitter rec: receiver mst/trx mode s1sta value 08h a start condition has been transmitted 10h a repeated start condition has been transmitted 18h sla and w have been transmitted, ack received 20h sla and w have been transmitted, ack received 28h data of s1dat has been transmitted, ack received 30h data of s1dat has been transmitted, ack received 38h arbitration lost in sla, r/w or data mst/rec mode s1sta value 08h a start condition has been transmitted 10h a repeated start condition has been transmitted 38h arbitration lost while returning ack 40h sla and r have been transmitted, ack received 48h sla and r have been transmitted, ack received 50h data has been received, ack returned 58h data has been received, ack returned slv/rec mode s1sta value 60h own sla and w have been received, ack returned 68h arbitration lost in sla, r/w as mst. own sla and w have been received, ack returned 70h general call has been received, ack returned 78h arbitration lost in sla, r/w as mst. general call has been received 80h previously addressed with own sla. data byte received, ack returned 88h previously addressed with own sla. data byte received, ack returned 90h previously addressed with general call. data byte has been received, ack has been returned 98h previously addressed with general call. data byte has been received, ack has been returned a0h a stop condition or repeated start condition has been received while still addressed as slv/rec or slv/trx slv/trx mode s1sta value a8h own sla and r have been received, ack returned b0h arbitration lost in sla, r/w as mst. own sla and r have been received, ack returned b8h data byte has been transmitted, ack received c0h data byte has been transmitted, ack received c8h last data byte has been transmitted (aa = logic 0), ack received miscellaneous s1sta value 00h bus error during mst mode or selected slv mode, due to an erroneous start or stop condition f8h no relevant state interruption available, si = 0. s1dat (dah) data shift register 76 543210 data shift register s1dat this register contains the serial data to be transmitted or data that has just been received. bit 7 is transmitted or received first, i.e., data is shifted from left to right. s1adr (dbh) slave address register 76 543210 s1adr.0, gc: 0 = general call address is not recognized 1 = general call address is recognized s1adr.7-1: own slave address this 8-bit register may be loaded with the 7-bit slave address, to which the controller will respond when programmed as a slave receiver/transmitter. the lsb bit (gc) is used to determine whether the general call address is recognized. table 3. scl frequency bit rate (khz) at f osc cr2 cr1 cr0 f osc divided by 3.58mhz 6mhz 12mhz 0 0 0 256 14.0 23.4 46.9 0 0 1 224 16.0 26.8 53.6 0 1 0 192 18.6 31.3 62.5 0 1 1 160 22.4 37.5 75.0 1 0 0 960 3.73 6.25 12.5 1 0 1 120 29.8 50 100 1 1 0 60 59.7 100 1 1 1 not allowed
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 11 interrupt system external events and the real-time-driven on-chip peripherals require service by the cpu asynchronous to the execution of any particular section of code. to tie the asynchronous activities of these functions to normal program execution, a multiple-source, two-priority level, nested interrupt system is provided. the 8xcl410 acknowledges interrupt requests from thirteen sources, as follows: int0 and int1 timer 0 and timer 1 i 2 c-bus serial i/o interrupt int2 to int9 (port 1) each interrupt vectors to a separate location in program memory for its service routine. each source can be individually enabled or disabled by corresponding bits in the internal enable registers (ien0, ien1) the priority level is selected via the interrupt priority register (ip0, ip1). all enabled sources can be globally disabled or enabled. external interrupts int2int9 port 1 lines serve an alternative purpose as eight additional interrupts int2int9. when enabled, each of these lines can awake-upo the device from power-down mode. using the ix1 register, each pin may be initialized to either active high or low. irq1 is the interrupt request flag register. each flag, if the interrupt is enabled, will be set on an interrupt request but it must be cleared by software. ien0 (a8h) interrupt enable register ea e es1 e et1 ex1 et0 ex0 76543210 bit symbol function ien0.7 eea general enable/disable control 0 = no interrupt is enabled 1 = any individually enabled interrupt will be accepted ien0.6 e (unused) ien0.5 es1 enable i 2 c sio interrupt ien0.4 e (unused) ien0.3 et1 enable timer t1 interrupt ien0.2 ex1 enable external interrupt 1 ien0.1 et0 enable timer t0 interrupt ien0.0 ex0 enable external interrupt 0 ien1 (e8h) interrupt enable register ex9 ex8 ex7 ex6 ex5 ex4 ex3 ex2 76543210 bit symbol function ien1.7 ex9 enable external interrupt 9 ien1.6 ex8 enable external interrupt 8 ien1.5 ex7 enable external interrupt 7 ien1.4 ex6 enable external interrupt 6 ien1.3 ex5 enable external interrupt 5 ien1.2 ex4 enable external interrupt 4 ien1.1 ex3 enable external interrupt 3 ien1.0 ex2 enable external interrupt 2 where 0 = interrupt disabled 1 = interrupt enabled ip0 (b8h) interrupt priority register e e ps1 e pt1 px1 pt0 px0 76543210 bit symbol function ip0.7 e (unused) ip0.6 e (unused) ip0.5 ps1 i 2 c sio interrupt priority level ip0.4 e (unused) ip0.3 pt1 timer 1 interrupt prioity level ip0.2 px1 external interrupt 1 priority level ip0.1 pt0 timer 0 interrupt prioity level ip0.0 px0 external interrupt 0 priority level ip1 (f8h) interrupt priority register px9 px8 px7 px6 px5 px4 px3 px2 76543210 bit symbol function ip1.7 px9 external interrupt 9 priority level ip1.6 px8 external interrupt 8 priority level ip1.5 px7 external interrupt 7 priority level ip1.4 px6 external interrupt 6 priority level ip1.3 px5 external interrupt 5 priority level ip1.2 px4 external interrupt 4 priority level ip1.1 px3 external interrupt 3 priority level ip1.0 px2 external interrupt 2 priority level interrupt priority is as follows: 0 low priority 1 high priority ix1 (e9h) interrupt polarity register il9 il8 il7 il6 il5 il4 il3 il2 76543210 bit symbol function ix1.7 il9 external interrupt 9 polarity level ix1.6 il8 external interrupt 8 polarity level ix1.5 il7 external interrupt 7 polarity level ix1.4 il6 external interrupt 6 polarity level ix1.3 il5 external interrupt 5 polarity level ix1.2 il4 external interrupt 4 polarity level ix1.1 il3 external interrupt 3 polarity level ix1.0 il2 external interrupt 2 polarity level writing either a a1o or a0o to an ix1 register bit sets the priority level of the corresponding external interrupt to active high or low, respectively.
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 12 irq1 (c0h) interrupt request flag register iq9 iq8 iq7 iq6 iq5 iq4 iq3 iq2 76543210 bit symbol function irq1.7 iq9 external interrupt 9 request flag irq1.6 iq8 external interrupt 8 request flag irq1.5 iq7 external interrupt 7 request flag irq1.4 iq6 external interrupt 6 request flag irq1.3 iq5 external interrupt 5 request flag irq1.2 iq4 external interrupt 4 request flag irq1.1 iq3 external interrupt 3 request flag irq1.0 iq2 external interrupt 2 request flag priority vector source x0 (highest) 0003h external 0 s1 002bh i 2 c port x5 0053h external 5 t0 000bh timer 0 x6 005bh external 6 x1 0013h external 1 x2 003bh external 2 x7 0063h external 7 t1 001bh timer 1 x3 0043h external 3 x8 006bh external 8 x4 004bh external 4 x9 (lowest) 0073h external 9 sfr register function address ix1 interrupt polarity register e9h irq1 interrupt request flag c0h register ien0 interrupt enable register a8h ien1 interrupt enable register e8h (int2int9) ip0 interrupt priority register b8h ip1 interrupt priority register f8h (int2int9) oscillator circuitry the on-chip oscillator circuitry of the 8xcl410 is a single stage inverting amplifier biased by an internal feedback resistor. (see figure 4.) the oscillator can be operated with a quartz crystal, ceramic resonator, lc network or rc network. see figure 5 for different configurations. when ordering parts, it is necessary to specify an oscillator option. the options are: rc when an rc network will be used, osc 2 for oscillator operation below 4mhz, osc 3 for oscillator operation from 4mhz to 10mhz, osc 4 for oscillator operation above 10mhz, and 32khz if 32khz to 400khz operation is desired. for operation as a standard quartz oscillator, no external components are needed (except at 32khz). when using external capacitors, ceramic resonators, coils, and rc networks to drive the oscillator, five different configurations are supported (see figure 5 and table 4). in the power-down mode the oscillator is stopped and xtal1 is pulled high. the oscillator inverter is switched off to ensure no current will flow. to drive the device with an external clock source, apply the external clock signal to xtal1, and leave xtal2 to float, as shown in figure 5(f). there are no requirements on the duty cycle of the external clock, since the input to the internal clocking circuitry is split using a flip-flop. the following options are provided for optimum on-chip oscillator performance. please state option when ordering: osc.1: figure 5(c). an option for 32khz clock applications with external trimmer for frequency adjustment. a 4.7m w bias resistor must be connected in parallel with the crystal. osc.2: figure 5(e). an option for low-power, low-frequency operations using lc components or quartz. osc.3: an option for medium frequency range applications. osc.4: an option for high frequency range applications. rc: figure 5(g). an option for an rc oscillator. the equivalent circuit data of the internal oscillator compares with that of matched crystals. the externally adjustable rc oscillator has a frequency range from 100khz to 500khz. (see figure 7.) power-on reset the 8xcl410 contains on-chip circuitry which switch the port pins to the customer-defined logic level as soon as v dd exceeds 1.3v if the mask option aono has been chosen (see figures 8 and 9). as soon as the minimum supply voltage is reached, the oscillator will start up. however, to ensure that the oscillator is stable before the controller starts, the clock signals are gated away from the cpu for a further 1536 oscillator periods. an hysteresis of approximately 50mv at a typical power-on switching level of 1.3v will ensure correct operation. the on-chip poweron reset circuitry can also be switched off via the mask option aoffo. this option reduces the power-down current to typically 800 m a and can be chosen if external reset circuitry is used. for applications not requiring the internal reset, option aoffo should be chosen. an automatic reset can be obtained at power-on by connecting the rst pin to v dd via a 10 m f capacitor. at power-on, the voltage on the rst pin is equal to v dd minus the capacitor voltage, and decreases from v dd as the capacitor discharges through the internal resistor r rst to ground. the larger the capacitor, the more slowly v rst decreases. v rst must remain above the lower threshold of the schmitt trigger long enough to effect a complete reset. the time required is the oscillator start-up time, plus 2 machine cycles. p80cl410: rom-less version of p83CL410 the p80cl410 is a low voltage romless version of the p83CL410. the mask options on the p80cl410 are fixed as follows: ? port options: all ports except p16/p17 have option a1so, i.e., standard port, high after reset. the ports p16/p17 have option a2so, i.e., open drain, high after reset. ? oscillator option: osc3 ? power-on reset option: off
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 13 figure 4. oscillator v dd v dd pd to internal timing circuits c1 i c2 i r bias xtal1 xtal2 v dd xtal1 xtal2 xtal1 xtal2 xtal1 xtal2 4.7 meg xtal1 xtal2 xtal1 xtal2 n.c. xtal1 xtal2 (a) oscillator configuration for quartz crystal (b) quartz oscillator with external capacitors (d) configuration for ceramic resonator (c) configuration for 32khz operation (e) configuration for lc network (f) external clock configuration (g) rc network configuration figure 5. oscillator configurations n.c. v dd
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 14 table 4. oscillator type selection guide c1 ext. c2 ext. maximum resonator resonator f (mhz) option min max min max series resistance quartz 0.032 osc.1 5 15 0 0 15k w 1 quartz 1.0 osc.2 0 30 0 30 600 w quartz 3.58 osc.2 0 15 0 15 100 w quartz 4.0 osc.2 0 20 0 20 75 w quartz 6.0 osc.3 0 10 0 10 60 w quartz 10.0 osc.4 0 15 0 15 60 w quartz 12.0 osc.4 0 10 0 10 40 w quartz 16.0 osc.4 0 15 0 15 20 w pxe 0.455 osc.2 40 50 40 50 10 w pxe 1.0 osc.2 15 50 15 50 100 w pxe 3.58 osc.2 0 40 0 40 10 w pxe 4.0 osc.2 0 40 0 40 10 w pxe 6.0 osc.2 0 20 0 20 5 w pxe 10.0 osc.3 0 15 0 15 6 w pxe 12.0 osc.4 10 40 10 40 6 w lc osc.2 20 90 20 90 10 m h = 1 w 100 m h = 5 w 1mh = 75 w note: 1. 32khz quartz crystals with a series resistance higher than 15k w will reduce the guaranteed supply voltage range to 2.5 to 3.5v. table 5. oscillator equivalent circuit parameters (see figure 6) parameter option symbol condition min typ max unit transconductance osc.1 g m t = +25 c; v dd = 4.5v 15 m s osc.2 g m t = +25 c; v dd = 4.5v 200 600 1000 m s osc.3 g m t = +25 c; v dd = 4.5v 400 1500 4000 m s osc.4 g m t = +25 c; v dd = 4.5v 1000 4000 10000 m s input capacitance osc.1 c1 i 3.0 pf osc.2 c1 i 8.0 pf osc.3 c1 i 8.0 pf osc.4 c1 i 8.0 pf output capacitance osc.1 c2 i 23.0 pf osc.2 c2 i 8.0 pf osc.3 c2 i 8.0 pf osc.4 c2 i 8.0 pf output resistance osc.1 r2 3800 k w osc.2 r2 65 k w osc.3 r2 18 k w osc.4 r2 5.0 k w
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 15 figure 6. equivalent circuit diagram xtal1 r f xtal2 c2 i c1 i v 1 g m r 2 figure 7. frequency as a function of rc 600 f osc ( khz) 400 200 0 02 4 6 rc ( m s) figure 8. power-on reset switching level start-up time 1536 oscillator periods delay supply voltage power-on reset (internal) oscillator cpu running switching level pdr hysteresis
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 16 figure 9. recommended power-on reset circuitry v cc 10 m f + v cc rst r rst 8xcl410 absolute maximum ratings 1, 2, 3 parameter rating unit supply voltage 0.5 to +6.5 v all input voltages 0.5 to v dd +0.5 v dc current into any input or output 5 ma total power dissipation 300 mw storage temperature range 65 to +150 c operating ambient temperature range 40 to +85 c operating junction temperature 125 c notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteristics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted.
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 17 dc electrical characteristics t amb = 40 c to +85 c, v ss = 0v test limits symbol parameter conditions min max unit v dd supply voltage f clk (see figure 13) 1.8 6.0 v ram retention voltage in power-down mode 1.0 e v i dd power supply current: operating 1 osc 1 option f clk = 32khz, v dd = 1.8v, t amb = +25 c e 50 m a osc 2 option f clk = 3.58mhz, v dd = 3v e 2.5 ma osc 2 option f clk = 10mhz, v dd = 5v e 14 ma osc 3 option f clk = 12mhz, v dd = 5v e 16 ma osc 4 option f clk = 12mhz, v dd = 5v e 20 ma idle mode 2 osc 1 option f clk = 32khz, v dd = 1.8v, t amb = +25 c e 25 m a osc 2 option f clk = 3.58mhz, v dd = 3v e 1.0 ma osc 2 option f clk = 10mhz, v dd = 5v e 5.0 ma osc 3 option f clk = 12mhz, v dd = 5v e 7.0 ma osc 4 option f clk = 12mhz, v dd = 5v e 8.5 ma power-down mode 3 v dd = 1.8v, t amb = +25 c e 10 m a v il input low voltage v ss 0.3v dd v v ih input high voltage 0.7v dd v dd v i ol output sink current, except sda, scl v dd = 5v, v ol = 0.4v 1.6 ma v dd = 2.5v, v ol = 0.4v 0.7 ma i ol1 output sink current, sda, scl v dd = 5v, v ol = 0.4v 3.0 ma i oh output source current (push-pull options only) v dd = 5v, v oh = v dd 0.4v 1.6 ma v dd = 2.5v, v oh = v dd 0.4v 0.7 ma i il logical 0 input current, ports 1, 2, 3 v dd = 5v,v in = 0.4v 100 m a v dd = 2.5v,v in = 0.4v 50 m a i tl logical 1-to-0 transition current, ports 1, 2, 3 v dd = 5v, v in = v dd /2 1.0 ma v dd = 2.5v, v in = v dd /2 500 m a i li input leakage current, port 0, ea v ss < v i < v dd 10 m a r rst internal reset pull-down resistor 10 200 k w notes: 1. the operating supply current is measured with all output pins disconnected; xtal1 driven with t r = t f = 10ns; v il = v ss , v ih = v dd ; xtal2 not connected; ea = rst = port 0 = v dd ; all open drain outputs connected to v ss . 2. the idle supply current is measured with all output pins disconnected; xtal1 driven with t r = t f = 10ns; v il = v ss , v ih = v dd ; xtal2 not connected; ea = port 0 = v dd ; rst = v ss ; all open drain outputs connected to v ss . 3. the power-down current is measured with all output pins disconnected; xtal1 not connected; ea = port 0 = v dd ; rst = v ss ; all open-drain outputs connected to v ss . 4. the rc-oscillator is not implemented in this version. 5. circuits with apower-on reseto option aoffo are tested at v ddmin = 1.8v, with option aono (typically 1.3v) are tested at v ddmin = 2.3v.
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 18 32khz 1.2mhz 1.6 1.8 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0123456 v dd min = 1.8v v dd (v) i dd (ma) typical operating current versus supply and frequency (32khz1.2mhz) at +25 c
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 19 ac electrical characteristics t amb = 40 c to +85 c, v ss = 0v 1, 2 12mhz clock variable clock symbol figure parameter min max min max unit program memory 1/t clcl oscillator frequency 0 20 mhz t ll 10 ale pulse width 127 2t clcl 40 ns t al 10 address valid to ale low 43 t clcl 40 ns t la 10 address hold after ale low 48 t clcl 35 ns t liv 10 ale low to valid instruction in 233 4t clcl 100 ns t lc 10 ale low to psen low 58 t clcl 25 ns t cc 10 psen pulse width 215 3t clcl 35 ns t civ 10 psen low to valid instruction in 125 3t clcl 125 ns t ci 10 input instruction hold after psen 0 0 ns t cif 10 input instruction float after psen 63 t clcl 20 ns t avi 10 address to valid instruction in 302 5t clcl 115 ns t afc 10 psen low to address float 0 0 ns data memory t rr 11 rd pulse width 400 6t clcl 100 ns t ww 12 wr pulse width 400 6t clcl 100 ns t la 11, 12 address hold time after ale 48 t clcl 35 ns t rd 11 rd low to valid data in 250 5t clcl 165 ns t dfr 11 data float after rd 97 2t clcl 70 ns t ld 11 ale low to valid data in 517 8t clcl 150 ns t ad 11 address to valid data in 585 9t clcl 165 ns t lw 11, 12 ale low to rd or wr low 200 300 3t clcl 50 3t clcl +50 ns t aw 11, 12 address valid to wr low or rd low 203 4t clcl 130 ns t dwx 12 data valid to wr transition 23 t clcl 60 ns t dw 11 data valid to wr 433 7t clcl 150 ns t wd 12 data hold after wr 33 t clcl 50 ns t afr 11 rd low to address float 3 12 12 ns t whlh 11, 12 rd or wr high to ale high 43 123 t clcl 40 t clcl +40 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 50pf, load capacitance for all other outputs = 40pf. 3. interfacing the 8xcl410 to devices with float time up to 75ns is permitted. this limited bus connection will not cause damage to port 0 drivers.
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 20 t lc t cif figure 10. external program memory read cycle ale psen port 0 port 2 a8a15 a8a15 a0a7 a0a7 t al t ci t la instr in t civ t ll t cc t liv t afc t avi t dfr ale psen port 0 port 2 figure 11. external data memory read cycle rd a0a7 from ri or dpl data in a0a7 from pcl instr in p2.0p2.7 or a8a15 from dph a8a15 from pch t whlh t ld t lw t rr t afr t aw t ad t rd t la t al
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 21 ale psen port 0 port 2 figure 12. external data memory write cycle wr a0a7 from ri or dpl data out a0a7 from pcl instr in p2.0p2.7 or a8a15 from dph a8a15 from pch t whlh t lw t ww t aw t dwx t wd t al t la t dw 0.9 v dd figure 13. ac testing input waveform test points 0.4 v dd 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd figure 14. input current i tl i il i il 500 m a 100 m a 0 v dd /2 v dd
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 22 figure 15. frequency operating range v dd (v) figure 16. typical operating current as a function of frequency and v dd , t amb = 25 c f (mhz) 01234567 100 10 1 0.1 0.01 note: below 32khz, clock has to be supplied externally. 16 12 8 4 0 12 4 6 12mhz 3.58mhz 8mhz v dd (v) i dd (ma) 35 3 1 5 4 2 6 8 4 2 0 2 4 6 1 3 5 v dd (v) i pd ( m a) 0 2 4 6 1 3 5 v dd (v) (ma) f idle figure 17. typical idle current as a function of frequency and v dd , t amb = 25 c figure 18. typical power-down current vs. frequency and v dd , t amb = 25 o c 0 12mhz 8mhz 3.58mhz
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 23 piggyback specification the differences between the masked version and the piggyback are described herein. general description the p85cl000hfz is a piggy-back version with 256 bytes of ram used for emulation of the p83CL410 microcontroller. the p85cl000hfz is manufactured in an advanced cmos technology. the instruction set of the p85cl000hfz is based on that of the 8051. the device has low power consumption and a wide supply voltage range. the p85cl000hfz has two software selectable modes of reduced activity for further power reduction: idle and power-down. for timing and ac/dc characteristics, please refer to the p83CL410 specifications. features ? full static 80c51 cpu ? 8-bit cpu, ram, i/o in a single 40-lead dip ? socket for up to 16k external eprom ? 256 bytes ram, expandable externally to 64k bytes ? four 8-bit ports, 32 i/o lines ? two 16-bit timer/event counters ? external memory expandable up to 128k, external rom up to 64k and/or ram up to 64k ? thirteen source, thirteen vector interrupt structure with two priority levels ? full duplex serial port (uart) ? i 2 c-bus interface for serial transfer on two lines ? enhanced architecture with: non-page oriented instructions direct addressing four eight byte ram register banks stack depth up to 128 bytes multiply, divide, subtract and compare instructions ? stop and idle instructions ? wake-up via external interrupts at port 1 ? single supply voltage of 1.8v to 6.0v ? on-chip oscillator (option: oscillator 4) ? very low current consumption ? operating temperature range: 40 to +85 c standard piggyback types: p85cl000hfz emulation for: p83CL410, p80cl51 list of differences between masked microcontroller and corresponding piggyback: parameter masked controller piggyback ram size 128 256 rom size 4k eprom size dependent (max 16k) port option 1, 2, 3 1 oscillator option osc. 1, 2, 3, 4, rc osc. 4 mech. dimensions standard dual in-line, small outline see sot158a current cons. i dd i dd (osc. 4) + i eprom voltage range full full, limited by eprom esd specification not tested (different package) purchase of philips i 2 c components conveys a license under the philips' i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011.
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 24 dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 25 vso40: plastic very small outline package; 40 leads sot158-1
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 26 qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c 1995 jan 20 27 notes
philips semiconductors product specification 80cl410/83CL410 low voltage/low power single-chip 8-bit microcontroller with i 2 c philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appliances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonably be expected to result in a personal injury. philips semiconductors and philips electronics north america corporation customers using or selling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors and philips electronics north america corporation register eligible circuits under the semiconductor chip protection act. ? copyright philips electronics north america corporation 1995 all rights reserved. printed in u.s.a. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.

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